On the Design and Implementation of a High Performance Configurable Architecture for Testor Identification

Typical testors are a useful tool to do feature selection in supervised classification problems with mixed incomplete data. However, the complexity of computing all typical testors of a training matrix has an exponential growth with respect to the number of columns in the matrix. For this reason different approaches like heuristic algorithms, parallel and distributed processing, have been developed. In this paper, we present a configurable custom architecture for the efficient identification of testors from a given input matrix. The architectural design is based on a brute force approach that is suitable for high populated input matrixes. The architecture has been designed to deal with parallel processing and can be configured for any size of matrix. The architecture is able to evaluate if a vector is a testor of the matrix in a single clock cycle. The architecture has been implemented on a Field Programmable Gate Array (FPGA) device. Results show that it provides runtime improvements over software implementations running on state-of-the-art processors. FPGA implementation results are presented and implications to the field of pattern recognition discussed.